Chapter 2

The Promise of Nanotechnology

Definition. On December 29, 1959, the Nobel Laureate Richard P. Feynman gave a landmark talk to the American Physical Society meeting, held that year at Caltech, that opened the door - and many eyes - to the small world of seemingly bottomless possibilities. In this talk entitled, "There's Plenty of Room at the Bottom," he invited his audience to enter a new field of physics. [1] At that time excitement over miniaturization was fairly new with researchers touting electric motors the size of a fingernail. He referenced a boast made of a device capable of writing the Lord's Prayer on the head of a pin - and then proceeded to explain how primitive and extremely limited this device really was relative to the potential available. In the realm of the Very Small, the head of a pin actually has room for the entire Encyclopedia Britannica! In addition, he went on to show that if a "bit" of information were represented by a cube comprising five atom per side, then the sum accumulation of all of the books in the world would come to 10¹⁵ bits, which could be packed into a volume smaller than 0.15 millimeter per side - the size of a spec of dust.

At the beginning of the 1960s when computers filled rooms, Feynman suggested that their circuits could be made of components and wires of only a few hundred nanometers that could lead to improving their capabilities by several orders of magnitude. He even hinted at possible computer sentience! Although he never called it by name, he nonetheless threw down the gauntlet and challenged his audience of physicists and chemists to boldly enter the world of nanotechnology. Indeed, there is plenty of room at the bottom!

Nanotechnology, as the name implies, is the application of an ability to design, fabricate, and control components, devices, and systems on the nanometer scale, where a nanometer is one billionth of a meter, or 10^-9 meter. A nanometer spans the width of approximately seven atoms. If a nanometer were one inch, then one inch would be 400 miles! This analogy gives one a much better perspective of how truly small these dimensions really are. Structures and systems with feature sizes below 100 nanometers that dwell in the region between individual atoms and bulk materials are considered to be in the realm of nanotechnology. The selection of 100 nanometers is considered to be the critical scale length, and at least one dimension of the component being studied must be within that dimension. Scale has a profound effect on physical behavior. As the size of a structure becomes diminishingly smaller, new properties of matter begin to emerge that are not necessarily predictable from the macroscale. Bulk material effects seen at the macroscale give way to surface effects. Not only is the diminishing size modifying characteristics that influence behavioral changes, but also unexpected features from quantum effects begin to emerge and in many cases dominate as materials approach the nanoscale. The ability to control these feature sizes and configurations enables the enhancement of device functions and component properties to take advantage of these new effects.

More than twenty years after Feynman's talk were to pass before instruments of sufficient capability, such as scanning tunneling microscopes and atomic force microscopes, were available to provide adequate capability to explore the nano-world. But once these new tools came into being, renewed excitement in this field was sparked throughout the scientific community. At last, researchers had the necessary means to measure and manipulate structures on a nanoscale. If credit were to be given to a single person for renewing the enthusiasm in this very dynamic field, it would likely go to Eric Drexler [2] who in 1987, armed with knowledge of the latest tools, expounded on the enormous ramifications of being able to manipulate matter on the molecular scale. He is also credited with having coined the term. Since that time, numerous futurists have grasped the implications of the nanotechnology impact when speculating what effect this new technology will have on life to come. [3-7] Nanotechnology offers a completely new paradigm for the fabrication of devices and structures by enabling their assemblies from the bottom up rather than by the conventional method of top down. Furthermore, these bottom-up constructions can take advantage of self-organization and self-assembly techniques. Science is only now beginning to understand but a few of the principles involved in the creation of nanosystems, and considerably more research is required. The field of nanotechnology is growing and changing so rapidly that publications merely a few years old, save for their historical interest, are becoming of limited value. Nanotechnology affects all disciplines benefiting from size reductions beyond miniaturization: examples include microelectronics and microintegrated circuits, biophysics, atomic physics, micromachines, and polymer chemistry to name a few. This is truly a new domain in science and technology.

Nanoelectronics. But the field of nanotechnology as it relates to this thesis resides almost exclusively in the realm of nanoelectronics and the impact that these new technologies will have on the evolution of a new class of computer. Explorations into the world of nanoelectronics have been exploding. Continued developments in nanosystems will enable the packaging of orders of magnitude more electronic components within the same volumes presently occupied by today’s microprocessors. Furthermore, miniaturization of these and other components to nano-sizes enables application of different principles of physics to achieve the same end, principles not admissible in the macroscopic scale. Nano-microprocessors, or “nanoprocessors,” will become a reality, and their wiring will be dendrites that are “grown” as required. The application of these nanoprocessors will introduce a new dimension space into the world of information processing – complexity. As multiple nanosystems are clustered and interfaced by more proficient system integrations, the processing sophistication – especially that of artificial neural networks – will increase enormously. This thesis addresses how nanotechnology, as it becomes more universally applied to information processing, will lead to an inherent complexity, comprised of nanoelectronics and subject to all of the resultant behavioral characteristics of such systems. But first let us review the factors that have motivated interest in the development of nanoelectronics.

Microprocessors. When Jack Kilby demonstrated the first microchip integrated circuit on September 12, 1958, he revolutionized the electronics paradigm and changed its course forever. [8] His invention led to the development of the microprocessor, which represented the state of the art of electronic integrated circuits at the beginning of the Twenty-First Century. The microprocessor is an electronic logic chip the size of one’s thumbnail comprising literally millions of microscopic transistors. Microprocessors, a term often used interchangeably with Very Large-Scale Integrated circuit (VLSI) and even sometimes with Central Processing Unit (CPU), are the core intelligence of the modern computer. By taking advantage of Moore’s Law, which states that the continued pace of microchip change is such that the microprocessor computing capability doubles every 18 months, industrialized nations have become very heavily dependent upon microelectronics for countless applications. On the order of 100 million transistors can be placed on but a few square centimeters of silicon, with the smallest features measuring approximately 180 nanometers. Industry projections suggest that this size will have shrunk to around 120 nanometers in another dozen years. [9]

Since Moore’s Law is most relevant to the augments developed in this thesis, it warrants further discussion. Gordon Moore, after whom the law is named, is a co-founder of Intel Corporation and at the time of this writing was its chairman emeritus. In 1964 he identified an empirical relationship between time and the number of transistors that could be integrated within a silicon microchip. In that year, he observed that the amount of information storable on a given integrated circuit doubled annually since the technology was invented. [10] This trend held until the late 1970s, wherein the doubling period slowed to every 18 months where it has remained through the end of the Century. Furthermore, the law also describes a relationship between this development time and the cost of the integrated circuit. The cost of the new microchips is observed to decrease by approximately 30% as the number of components on them doubles.

Several factors contributed to this relentless pace of microprocessor development. First, an environment that strongly encouraged this industry was fostered. There was ready access to capital, the creation of open organizations that stimulated innovation, and the acceptance of a paradigm where the only constant is change. But with the dynamic economic factors and the enormous market it created once it came to be established, it became – as Gordon Moore himself pointed out – a self-fulfilling prophesy. Moore’s Law is the reference standard today for the rate of change of growth in microprocessor technology, as the semiconductor industry must adhere to this curve if it is to remain competitive. The resulting products, however, have been nothing short of wondrous. In 1979 a typical desktop computer boasted 16 kilobits of random-access memory (RAM), 128 kilobits of hard-drive memory, a processor speed of two megahertz, which one could obtain at a cost of $5000. In 1997 for $1400 one could buy a desktop computer that had 12 megabits of RAM, a 750-megabit hard-drive memory, and a processor speed of 150 megahertz. Intel Corporation projects that by the year 2010 RAM will be three gigabits, the hard-drive memory will be over 200 gigabits, and the processor speed will approach 10 gigahertz. As incredible as this may sound, one needs only to observe that today (mid 2002) 20-gigabit hard drives and one-gigahertz chips are commonplace. Intel further predicts that by 2010 the microprocessor will comprise a billion transistors and will be capable of 100,000 million instructions per second (MIPS).

Progression in Electronic Miniaturization. The demand for faster, more capable electronics has motivated the development of ever-smaller devices and components, and research is continuously underway exploring yet additional alternatives. The microelectronics that make up the state of the art of microprocessors and microdevices are typically comprised of complementary metal oxide semiconductors, or CMOS. From the time of the development of the first metal oxide semiconductor by Texas Instruments in 1968, [11] CMOS technology has grown to represent greater than 75 percent of the world’s semiconductor market. As state-of-the-art technology for all digital-processing systems, it dominates the technological advancements for all other semiconductor products. The appeal of CMOS technology is that it lends itself so readily to miniaturization, and its manufacturing process is fairly straightforward. The scaling of deep submicron[1] CMOS transistors has progressed from dimensions on the order of 1000 nanometers of the early 1980s to having demonstrated 250-nanometer devices by the end of the century. Let us begin our venture into the world of the Very Small with a look at CMOS technology.

The miniaturization allowed by the CMOS process is primarily credited for the rapid advances in integrated-circuit technology responsible for the phenomenal growth experienced by the electronics industry over the past two decades. The applications of these integrated circuits have been rising steadily and rapidly in all areas of consumer electronics, but especially in high-performance computing where the need for faster, more capable computers has been the dominant driver. Consumer demands for very high processing power, increased bandwidth, and portability have maintained a relentless drive for smaller, more intelligent devices. This desire for more complex functions has necessitated the integration of a greater number of transistors into ever-smaller packages.

One metric of this integration is the number of logic gates packaged into a single monolithic chip, and the rapid progress in processing and interconnect technologies witnessed over the past thirty years has led to the rise of this packing density. The result has been an exponential increase in logic complexity per chip. There are a number of advantages for the monolithic integration of a large number of functions onto a single chip. Compactness is achieved from a reduced area per unit volume, less power is consumed, the improved on-chip interconnects result in higher reliability, the dramatically reduced interconnect length enables much higher speed, and there is significant cost savings. This trend of integration is expected to continue in the foreseeable future, supported by the steady reduction of the minimum feature size and other advances in device manufacturing technology. “Feature size” is defined as the characteristic length of the smallest whole feature realizable on a chip, such as the minimum length of a transistor or an interconnect.

The history of chip packaging shown in Figure 2.1 gives one a feel for the evolution of integration density and the steady decline of feature size experienced over the latter part of the Twentieth Century. This figure, generated in the mid 1980s, [12] projected a minimum feature size of 300 nanometers (0.3 microns) by the year 2000. In reality, this expectation was far exceeded with the routine production of 250 nanometer transistors and the demonstration of 180 nanometer feature sizes by the late 1990s. A direct result of this accelerated development was the exceeded projection of the chip integration density. An example of this was the Intel Pentium microprocessor that was introduced in 1994 and comprised over three million transistors.

When one speaks of an integrated circuit’s integration density, however, one must clearly differentiate between memory chips and logic chips. Logic chips contain many different functional units, in addition to large arrays of memory cells. Hence, they require very complex interconnects that consume a large portion of the chip’s area, resulting in significantly fewer transistors. This is not the case for memory chips with their highly regular circuits enabling more cells to be integrated with considerably less area taken up by interconnects.

Figure 2.2 depicts the dramatic growth in capability of the microprocessor chip since the early 1970s. Following Moore's Law with uncanny regularity, each new chip generation has succeeded in doubling it capacity, with a promise of delivering microprocessors with over 100 million transistors before 2005. This represents a factor of greater than ten thousand improvement in transistor density experienced over the past three decades - a truly remarkable feat.

CMOS Fabrication. This story is not complete without a discussion of the CMOS fabrication process so that one might gain better insight into both the wonder and the limitations of the technology that drove the modern microprocessor industry so far. It is the limitations of this process, as we will see later, that contribute most significantly to the theme of this thesis.

When one looks at the process flow and interaction of the various processing steps in CMOS fabrication technology, one must keep in mind that there is a very strong relationship between the fabrication process, the efforts of the circuit designers, and the resulting chip performance. Designers must be familiar with both the fabrication process and the various manufacturing steps so that optimum performance might be realized from the resulting chip. This discussion focuses solely on the fabrication.

A review of CMOS fabrication is an excellent way to obtain a better understanding of the intricate steps involved in a top-down production process for electronic devices. We will first look at the basic process steps for pattern transfer through lithography and go through an example fabrication process of a single n-channel metal oxide semiconductor, or MOS, transistor. [12] CMOS fabrication requires that both n-channel and p-channel transistors be assembled on the same silicon substrate. The n-channel and p-channel are often called nMOS and pMOS, where “n” and “p” refer to negative and positive charge, respectively. Special regions where the semiconductor type is opposite that of the substrate type, called “tubs” or more commonly “wells,” are created to accommodate both the nMOS and pMOS devices. In other words, an n-well is created in a p-type substrate and vice versa. For the basic n-well CMOS process being discussed, the nMOS transistor is produced within the p-type substrate and conversely for the pMOS transistor. A p-type substrate is one rich in positive ions so as to present a net positive charge. It insulates and blocks current flow between the “source” and “drain” contacts (discussed below) to provide the transistor “off” function. When a positive charge is applied to the transistor “gate,” it polarizes charge carriers in the silicon substrate to form a “channel” of negative charge that allows current to flow. In this state, the transistor is “on.” A very simplified overview of CMOS integrated-circuit fabrication can be seen in Figure 2.3. The process begins with the creation of the n-well and channel-stop regions, followed by the growth of first a thick-field oxide in the areas around the nMOS and pMOS and then a thin gate oxide. The process continues with the deposition and patterning of the polysilicon layer; then the source, drain, and channel-stops are implanted. The last steps are the creation of the contact windows and the final metalization to form the interconnects. These steps will become more clear in the discussion below.

Because each processing step in the production of a CMOS integrated circuit requires that certain areas be defined by specific masks, the final product could be viewed as a set of patterned layers. These layers comprise doped silicon, polysilicon, metal, and insulating silicon. Typically, a pattern is inlaid onto each layer prior to application of the next layer of material onto the chip, and this pattern-transfer process is called “lithography.” Because each of these patterns is different and distinct, the lithographic sequence must be repeated with a different mask for each layer put down.

To obtain a better feel for the complex assembly processes involved in the production of a CMOS microchip, one needs to review the steps required to produce a single microelectronic transistor such as a bulk-effect switch and amplifier. A very common methodology for patterning silicon dioxide is with optical lithography, and the process depicted in Figure 2.4 (d) shows how lithography is typically applied. First, the silicon surface is thermally oxidized to produce an oxide layer thickness of approximately 1000 nanometers. Next, the oxide surface is coated with a layer of acid-resistant, light-sensitive organic polymer called “photoresist.” The photoresist material is specifically chosen as being insoluble in the developing solution until exposed to ultraviolet light. This type of photoresist is termed “positive photoresist.” Another type of photoresist material that is initially soluble but hardens when exposed to ultraviolet light is called “negative photoresist.”[2] However, the use of negative photoresist in the fabrication of CMOS integrated circuits is much less common due to the poorer photolithographic resolution they produce. At this point the need for masking becomes more obvious. A mask with selectively designed opaque features is then overlaid onto the photoresist polymer coating, and the chip is exposed to ultraviolet light. The exposed areas are now soluble and can be removed with etching solvents. The shielded areas remain resistant. This can be seen in segment (d) of Figure 2.4.

Portions of the silicon dioxide not covered by hardened photoresist are then etched away by applying either a chemical solvent, typically hydrogen fluoride, or with a dry, plasma-etch process. This etching action removes material down to the pure silicon substrate, forming “windows” in the oxide coating. The leftover hardened photoresist is then stripped off with a different solvent, resulting in the configuration seen in Figure 2.4 (g). The process-step description detailed above represents the series of steps required to obtain a

Figure 2.4. Process steps required to etch the desired silicon-dioxide pattern for a single transistor. Step (g) is the final configuration. [12]

single-pattern transfer of the silicon dioxide layer onto the silicon substrate. Starting with the overlaid silicon dioxide in Figure 2.4 (b), the desired intermediate step-patterned structure is shown in Figure 2.4 (g).

Numerous subsequent pattern transfers performed on silicon dioxide, polysilicon, and metal are required in the fabrication of these n-type MOS transistors, and the masking process for all of these steps is very similar to that described above. In addition, electron beam lithography is often used in place of optical lithography for the accurate generation of high-density patterns needed for devices smaller than 1000 nanometers.

Now let us look at the processing steps required to fabricate an n-channel MOS transistor onto a p-type silicon substrate. The first step in this process is that described above, which has left us with a patterned silicon dioxide layer called “field oxide” overlaid onto the substrate. A thin layer of very high-quality oxide is then deposited over the field oxide. This layer will form the “gate oxide” of the MOS transistor. Next, a layer of polycrystalline silicone (polysilicon) is put down on top of the gate oxide. Polysilicon is commonly used both as a gate electrode material for MOS transistors and as an interconnect material in the microprocessors themselves. The normally high resistivity of pure polysilicon can be reduced and “tuned” for a specific application by doping it with an impurity. The unwanted areas of polysilicon are then etched away to form the MOS transistor gates and interconnects, as seen in Figure 2.5 (f). Etching continues to remove that segment of the gate oxide that interfaces with the silicon substrate adjacent to the remaining polysilicon until the intermediate step-pattern structure is reached (Figure 2.5, g). Now the “source” and “drain” junctions of the transistor can be developed. To accomplish this, the entire exposed silicon surface is doped with a high concentration of impurities. This doping is accomplished either through diffusion or through ion implantation, and for this example of n-type doping donor atoms are supplied. The doping material penetrates into the silicon substrate to form the two n-type locales – the source and drain junctions – in the p-substrate. The same doping substance also soaks into the polysilicon gate electrode and reduces its resistivity. Since the polysilicon was patterned prior to doping, it defines the specific location of the channel region and hence the location of the source and drain. Because of the very precise

Figure 2.5 (a). First series of steps in the process flow used in fabricating an n-type metal-oxide semiconductor transistor on p-type silicon. [12]

positioning of both the source and drain and the channel sections enabled by this process, the procedure is called the “self-aligned process.”

With the source and drain steps completed, the transistor surface is again overlaid with a silicon dioxide insulating area. And again that portion of the silicon dioxide covering the source and drain channels is etched away, leaving the silicon dioxide layer on the polysilicon gate electrode. The exposed source and drain surfaces are then covered with evaporated aluminum to form the interconnects. The transistor interconnections are finalized with the patterning and etching of the metal layer. Repeating the steps of depositing another layer of silicon dioxide, followed by etching, then the overlay and patterning of the metal layer is usually done. But for the purpose of this example, all of the above are the steps required to produce a single n-type MOS transistor. As a reminder, this is the same transistor whose characteristic length referred to earlier is on the order of 250 nanometers – one quarter of one millionth of a meter!

The more complex process of producing the complete n-well CMOS integrated-circuit microprocessor follows similar steps of layering, lithographic masking, etching, doping, relayering, and so on. In fact, the production of the integrated circuit is a macrocosm of the above description for the single transistor, as the microchips are obviously not fabricated by selecting a single transistor at a time. Specific additional steps are required to bring all of the individual components together into a final integrated product, but that procedure will not be discussed here. The point of the detailed description of the single transistor was to show how complicated the assembly process is and to attempt to generate an appreciation for how increasingly difficult the fabrication becomes as the size of the transistor gets smaller.

Physical Limitations. Unfortunately, silicon-based microelectronics fabricated in the manner described above cannot follow Moore’s Law forever. In 1997 Gordon Moore himself speculated that there were probably five more generations remaining before physical limitations are met. If a generation is taken as 18 months, then this could mean that the ability of the industry to double the computing power of a microchip within that period could conservatively begin a noticeable slowdown as early as the year 2005. [13] Chip fabrication will eventually encounter a wall of economic unfeasibility as further scaling down of microelectronics continues. Because of the different functions they perform, logic chips are a more complicated design than are memory chips. As a result, the design complexity increases nearly exponentially with the number of transistors to be integrated, and this in turn impacts the design-cycle time, causing a tendency for the actual integration level to fall short of the level potentially achievable with current technology. Physical limitations such as stray signals and heat-dissipation constraints will be encountered as more transistors are packed onto a chip, and the increasing magnitude of difficulty of creating ever-smaller devices will severely impact progress. Specialists in this technology expect these challenges to intensify dramatically as the transitions approach the 100 nanometer dimensions. [9] Because of these ever-increasing fabrication difficulties, the yin of the explosive increase in transistor densities and processing rates of improved integrated circuits projected by Moore’s Law is countered by the yang of the mounting costs required for facilities to produce the chips. An inevitable market equilibrium will be reached when the continually decreasing physical scale of the microelectronics reaches the rapidly increasing economic impact for their production. This impasse could be reached as early as 2015, when the cost of a facility required to fabricate these chips is projected to be nearly $200 billion. That event will signal the end of the long breathtaking advance in CMOS computer-chip processing power. It will have come to the end of its road, for beyond that point the cost of any further improvement in processing rates will be prohibitive.

The Holy Grail of computer science to produce a sophisticated electronic “brain” on par with humans in intellectual and cognitive ability will almost certainly be out of reach when this deadlock occurs – at least with the present methodology of microprocessor production. Small, dense, complex circuitry is required to give rise to true cognitive abilities, and few researchers believe that the present technology of semiconductor-based microelectronics could ever lead to that state. An estimate of the size of a CMOS-derived “microchip” required to produce a capability approaching that of the human brain would put this in perspective. Hans Moravec of the Carnegie Mellon Robotics Institute [14] has estimated that the brain, depicted as a massively parallel “computer,” is capable of performing 100 million million instructions per second, or 100 million MIPS. For comparison, a Pentium chip can perform but a mere 750 MIPS. Given that a Pentium microprocessor derived from the latest CMOS technology comprising submicron transistors as discussed earlier has an area of approximately 1 cm² (i.e., one centimeter on each side), a “microprocessor” produced with CMOS technology that is capable of the 100 million MIPS of the human brain would require an area of nearly 134,000 cm² – nearly 3.7 meters per side. In English units, the dimensions would be nearly 12 feet by 12 feet! And this size pertains only to the processor chip itself. Once the interconnections, supporting subsystems, and cooling requirements are added, the resulting configuration would be many times that size. It is obvious from the above that in order to produce a processor of human-brain capability much more radical miniaturization is required than can be derived from CMOS technology. Fortunately, through recent revolutionary advances in research wherein the technical feasibility of molecular-scale electronic devices has been demonstrated, a solution is at hand. [9, 15]

Molecular “Wires”. The production of microelectronic components by the CMOS process is a “top-down” procedure wherein the intent is to continually shrink elements comprising the microprocessors to their lowest practical limit. But what if components providing identical functions could be produced from the bottom up – in other words starting at the molecular level? If the basic elements of microprocessors could somehow be coded initially at the molecular level and synthesized for their specialty functions from that point, then orders-of-magnitude smaller systems could be realized.

The concept of fabricating nanoscale devices with molecules has spawned an enthusiastic research effort that probably traces its origin to the work performed in the early 1970s by chemist Ari Aviram of the IBM Thomas J. Watson Research Center in Yorktown Heights, N.Y., and Mark Ratner, a chemistry professor at Northwestern University. At that time they began envisioning how molecular electronic elements and devices could be synthesized and proposed a rectifier consisting of a single molecule. [16] Their calculations showed that a properly designed organic molecule could readily function as an electronic rectifier, a simple device that allows current to flow in only one direction. Twenty-three years after they specified the theoretical structure and function of a molecular diode switch, such a rectifier has demonstrated nearly ideal characteristics in the way it passed current preferentially in one direction. [17, 18] In 1997 Professor Robert Metzger and his colleagues at the University of Alabama produced the molecule named hexadecylquinolinium tricyanoquinodimethanide and measured the bi-directional current flow through it between two aluminum electrodes. The rectification ratio of these two currents, the ratio indicating the preferential flow direction, ranged from 2.4 to 26.4 for different room-temperature samples. These results demonstrated a definite preference for the direction of the electron flow. The chemical configuration of this molecule is shown in Figure 2.6.

Serious research has been underway in molecular electronics since the mid 1990s [19-21], and the fabrication and demonstration of a functioning molecular “wire” by Allara, Tour, and Weiss and their associates in 1996 represented a major advance in this endeavor. [19] An early objective of this research was to identify a specific molecule or class of molecules with the capability of being readily producible and of demonstrating a measurable, reproducible electrical conductivity. A molecular wire, as described by Bumm, et al. [19] can be thought of as conjugated molecules forming one-dimensional electronic conductors. These single-molecular conductors are designed to interconnect with such molecular electronic devices as molecular switches and single-electron transistors. Extensive research of numerous candidate molecules made possible by advanced microfabrication and self-assembly techniques has not only demonstrated this desired electrical conduction, but it has also demonstrated large reversible switching behavior where discrete molecules are the active component of an electronic device. [20] By using a nanoscale device area as the essential feature for their fabrication process, Chen et al. were able to produce a small number of self-assembled molecules while eliminating defects that would hamper electronic transport measurements through the monolayer. Furthermore, they achieved good control over the device area while creating and maintaining intrinsic contact stability. And they were able to produce a significant quantity of devices with a production yield acceptably large enough to make the results statistically significant. The enthusiastic progression of this research, and the promise it holds, is reminiscent of the reported breakthroughs and heartening projections announced in the early 1960s about the then new field of metal-oxide semiconductors!

But what are these devices specifically? To begin with, there are two classes of molecules that have demonstrated possession of the characteristics acceptable for molecular-scale electronic devices: carbon nanotubes and polyphenylene-based chains. Of the two, polyphenylene-based chains likely offer more promise for a near-term payoff. As a result, this selection has formed the backbone of much of the recent research into molecular electronic wire and devices, such as the conducting molecular wire demonstrated by Allara, Tour, and Weiss. [22] Polyphenylene is an organic molecule comprised of chains of aromatic benzene rings and is a much smaller molecule than is a carbon nanotube. The basic structure of this molecule is shown in Figure 2.7.

To get a feel for what is involved in producing a current carrier of such a small magnitude, let us first look at how one would produce a “simple” conductor or wire. If one removes two hydrogen atoms from a benzene ring (C₆H₆), one obtains a phenylene structure (C₆H₄), which is a ring with two bonding sites. Now if one bonds numerous phenylene groups together, with the missing hydrogen atoms acting as attraction sites, one can see how a chain of phenylene groups can be formed such as that depicted in Figure 2.7. The chain is terminated with a phenyl-group molecule, which is a benzene ring with only one hydrogen removed (C₆H₅). Because the resulting monofilament is of arbitrary length, it is called a “polyphenylene” chain, where “poly” means “more than one.” Other molecular groups can be adapted to this chain to specialize it for specific properties or characteristics that may be desired. For example, triply bonded ethynyl or acetylenic links are often inserted as spacers to eliminate interference from adjacent hydrogen atoms in order to enhance the conductivity of the molecular wire.

In regard to how well this “wire” conducts current, a controlled test performed at Yale University for a three-ring polyphenylene chain demonstrated approximately 30 x 10^-9 amperes of current passing through the molecule. [23] This figure was obtained from measurements of total current passage in a carefully prepared experiment comprising approximately 1000 identical three-ring polyphenylene-based chain molecules in parallel. The technique for synthesizing conductive polyphenylene-based chains has been refined by James Tour so well with great repeatability over the past few years that they have come to be known as “Tour wires.” [24, 25] Furthermore, other experiments with adding aliphatic methylene groups to the chain have shown this additive to be an excellent insulator. Depending upon where within the polyphenylene-based molecular wire it is added, aliphatic methylene could function either as a “resistor” or as an “insulator.”

Given the existence and demonstration of molecular wires, the development of molecular electronic “devices” is often, in principle at least, the bonding of a different set of molecules with specifically desired characteristics at a proper location within the chain. As mentioned above, an example of one such device is the simple diode, which is a two-terminal switch that ensures unidirectional flow of current by turning “off” if the current attempts to enter through the “out” terminal. Both rectifying diodes and resonant-tunneling diodes have been recently demonstrated. While the molecular rectifying diode, based on the work by Aviram and Ratner discussed earlier, has been successfully demonstrated by teams led by Metzger at the University of Alabama and Reed at Yale, [17, 18] to date the teams have found that these molecules do not readily integrate with “Tour wires” to produce a compact, well-defined molecular circuit. Although other configurations of polyphenylene-based molecular rectifier are being designed, [22] molecular-resonant tunneling diodes have been found to integrate rather nicely.

A resonant-tunneling diode is a quantum device that employs quantum effects in their simplest form by utilizing energy quantization for the “on”-“off” switching of an electric current. The energy quantization “regulates” the variation of voltage bias across the source and drain contacts of the diode. However, current can pass equally well in either direction for the resonant-tunneling diode, unlike that of the rectifier. In order to control the desired direction of the electron flow, a set of “insulators” acting as tunnel barriers are placed very close together to create a potential-energy “well” or “island.” Such closely spaced barriers restrict electron energies to one of a finite number of quantum states, as dictated by quantum mechanics. Electron flow occurs via quantum-mechanical “tunneling” through the two barriers. The probability that electrons can tunnel depends upon the difference between the energy level of the incoming electrons and that of the electrons within the potential well. (See Figure 2.8.) If the energy quantum state of the electrons arriving in the device is different from the energy level allowed inside the potential well, current flow is not allowed and the device is switched “off.” But if the energy quantum state of the arriving electrons matches one of the energy levels of the island barrier, a condition said to be “in resonance,” then the state of the device is “on” and current flows.

Again, Tour and Reed have pioneered the development of the resonant-tunneling diode and have produced the first working “prototype,” patterning it as a molecular analog of the much larger solid-state resonant-tunneling device. [26, 27] A depiction of this molecule with the resonant-tunneling diode in place is shown in Figure 2.8. By inserting two aliphatic methylene groups into the polyphenylene-based chain “wire” on either side of a single aliphatic ring, they were able to demonstrate a resonant-tunneling diode. Figure 2.8 depicts this as the “island” formed by the CH₂ or methylene group located on either side of the benzene ring. The aliphatic group insulating properties, mentioned earlier, now act as potential-energy barriers to the flow of electrons. The aromatic ring between the aliphatic groups provides a very narrow gap of approximately 0.5 nanometer, which becomes the region of lower potential energy that the electrons must pass through.

Because of the possibility of multiple quantum levels implicit with resonant-tunneling devices, the additional advantage of multistate switching behavior is permitted. A continuously increasing bias voltage can produce multiple energy levels that come into resonance with the incident electrons. This multiple switching behavior represents additional logic states for each device.

Similar progress has been experienced in the research of carbon nanotubes, also known as tubular fullerenes. A carbon nanotube, as depicted in Figure 2.9, is a cylinder of carbon atoms comprising a single molecule that measures from one to 20 nanometers (nominally 10 atoms) in diameter. Depending upon the growth process implemented, its length can vary from approximately 100 nanometers to several microns. Discovered in 1991 by Sumio Iijima while doing research at the NEC corporation on the C₆₀ carbon molecule called the buckminsterfullerene, carbon nanotubes can be either conductors or semiconductors – depending upon their “chiral” or twist angles and diameters. The possibility that combinations of these nanotubes could function both as a “wire” and as a semiconductor inspired research into making this so. [28-31] In 1997 Cees Dekker and his associates at the Delft University of Technology in the Netherlands were the first to demonstrate the capability of nanotubes to act as wires. The following year this same team demonstrated a transistor using a nanotube as one of its components. They then expanded their research into finding ways to adapt nanotubes as electronic devices and discovered that a kink in a nanotube caused it to act like a rectifier diode. [32] This discovery inspired research into methods of introducing local defects into nanotubes with the aid of an atomic force microscope as a means of specializing the molecule for a specific characteristic. Through manipulation of individual molecules, researchers at IBM Corporation have successfully produced an array of transistors out of carbon nanotubes. [33] IBM has been investigating the application of carbon nanotubes as replacements for silicon when the floor of size reduction for silicon chips is reached and further miniaturization by conventional means is no longer economically feasible. IBM researchers are optimistic that carbon nanotubes will at least match Moore’s Law improvements experienced by today’s silicon chips. While a technique for the self-ordering of both the conducting and semiconducting nanotubes has so far eluded researchers, the IBM team has discovered a technique for producing only semiconducting nanotubes through the destruction of the conductors. This is a significant step toward the practical application of nanotubes in computer chips.

This stage of research into molecular wire and electronic devices has produced an interesting tradeoff dichotomy. Full application of molecular electronics requires a flexible reaction chemistry capable of producing long strings with desired branch structures. But is also desires a high electrical conductivity for these large structures. While polyphenylenes provide the more flexible reaction chemistry, nanotubes are more conductive. However, the present state of research with nanotubes does not promise a near-term solution for providing strings of self-ordering structures desired for molecular electronic systems. Furthermore, for this thesis we have a special interest in the characteristics inherent with polypheylene-based chains motivated by the fact that these longer “string” molecules can be made to represent dendrites of an artificial neuron, to be discussed later.

Clearly there are tremendous technical challenges yet remaining in the development of nanoelectronic devices. But the important point of the above discussion is that such devices have already been demonstrated in the laboratory, thus proving their feasibility. Merely knowing that something is possible overcomes the greatest initial barrier to its development. On a grander scale is the overriding seriousness of this research. A significant portion of this research effort is funded by the Defense Advanced Research Projects Agency (DARPA) through a program DARPA calls the Molecular Electronics or Moletronics Program. The objective of the Moletronics Program is “to demonstrate the integration of molecules or nanoparticles into scalable, functional electronic devices that are connected to each other and to the outside world in a realistic and practical manner.” [34] Through this effort DARPA seeks to provide computational capability with high-density memory in an extremely small, low-power format – and to provide this capability with affordable fabrication facilities. DARPA’s specific thrust is in the development of molecular logic and memory devices. The logic devices, or molecular logic gates, are to operate at room temperature and demonstrate a configuration that is scalable to densities greater than 10¹² gates per square centimeter. The goal for the memory devices is that they be low-power, high-density, terabit memories that have functional 16-bit molecular memory at a density of 10¹⁵ bits per cubic centimeter. Furthermore, DARPA’s research initiative encourages the implementation of device and interconnect schemes with directed self-assembly techniques.

Size Comparison. The difference in the physical size of CMOS and molecular electronic devices is staggering and worthy of comment. First, let us consider that the lithographic linewidth used in state-of-the-art conventional CMOS is 250 nanometers, as discussed earlier. With this taken as a reference dimension, the scale of a typical simple electronic device such as an AND, OR, or Exclusive Or (XOR) logic gate is approximately 40 times larger than the lithographic line width per side. Hence, the device itself is 40 x 250 or 10,000 nanometers long and by the same amount wide, with a resulting area of 100 x 10⁶ square nanometers. Although this area is still microscopic, it is huge when compared with that of a molecular AND, OR, or XOR logic gate. The area of the equivalent molecular electronic device is on the order of 12 square nanometers – approximately eight million times smaller! [22] Even if the molecular device were ten times larger, it would still be on the order of a million times smaller than the state of the art of an equivalent conventional CMOS device. With the introduction of molecular electronic devices, miniaturization and component packaging become a completely different paradigm.

Now let us look again at the comparison with a Pentium processor. Earlier, we determined that a Pentium processor chip, a CMOS technology, has an area of approximately 1 cm² and can perform 750 MIPS (million instructions per second). From this information, we calculated that a chip area of 134,000 cm² was required to perform 100 million MIPS – the equivalent processing rate of the human brain. But what if the Pentium chip were comprised of molecular electronic devices with areas a million times smaller than their CMOS counterparts? Were this the case, then a “super” Pentium processor capable of achieving the same number of instructions as the human brain could be fabricated into a chip size smaller than 14% of the state-of-the-art Pentium! With the impossible now feasible and the unreachable now possible, we are limited only by our imaginations.

The Future of Nanoelectronics. When projecting the future, one has a natural tendency to perceive only evolutionary changes from the present status. But the total impact of nanotechnology on the future of electronics will very likely be much greater than was the influence of the silicon integrated circuit. The benefits that will ultimately evolve from learning how to tailor fundamental properties and phenomena at the nanoscale where chemical and quantum effects are defined will be astounding. With the capability of controlling the features of a desired component or structure during its basic molecular assembly, entirely new phenomena and behavioral characteristics amplified by quantum effects will emerge that had never before been imagined. The technological future with nanoelectronics will be revolutionary, spawning major new industries neither envisioned nor conjectured today. The technological revolution will involve the design and chemical synthesis of molecules that are quantum electronic devices. These quantum devices will self-organize and self-assemble into desired circuits by following encoded instructions based on simple principles yet to be discovered. The paradigm shift will be irreversible. Nanotechnology, especially in the realm of nanoelectronics, has the potential of changing the perspective of nearly every human endeavor for the remainder of the Twenty-First Century.

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[1] A micron is one millionth of a meter in length, a thousand times larger than a nanometer.

[2] Negative photoresist is commonly used by dentists for tooth-enamel repair.